The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As the scaling down process continues to advance, alignment and overlay issues become more important due to the ever-decreasing device sizes. A small alignment or overlay error during fabrication may lead to the failure of a wafer. In conventional semiconductor fabrication processes, various devices and techniques have been utilized to minimize misalignment during fabrication. For example, alignment marks may be used to ensure correct alignment between wafers as they are loaded into a semiconductor fabrication tool. As another example, a wafer leveling system may be used to ensure the wafer is flat during fabrication. However, particles generated by various fabrication processes may still cause alignment problems for conventional semiconductor fabrication processes, particularly if these particles are located on a back side of a wafer edge region. Consequently, the conventional semiconductor fabrication processes may produce failed wafers from time to time, thereby lowering yield and increasing fabrication costs.
Therefore, while existing semiconductor fabrication processes have been generally adequate for their intended purposes, they are not entirely satisfactory in every aspect.